1. Field of the Invention
The present invention generally relates to searchers for Code Division Multiple Access (CDMA) receiver apparatuses, and more particularly to a searcher which searches for a synchronizing timing with respect to a spreading code sequence within a received signal in a CDMA receiver apparatus.
When a CDMA system such as a Direct Sequence Code Division Multiple Access (DS-CDMA) system is applied to a mobile communication, it is essential to provide in a receiver apparatus a searcher function for detecting a timing of a despreading code by carrying out a path detection. In order to realize this searcher function, there are demands to reduce the number of bits of correlation value information which is obtained from a correlator output, and to provide substantially the same dynamic range or an improved dynamic range as compared to the conventional dynamic range.
2. Description of the Related Art
FIG. 1 is a system block diagram for explaining the operating principle of the CDMA system which is employed in a mobile communication or the like. As shown in FIG. 1, a transmitting end uses a modulator 81 to modulate information data having a rate of 10 kbps, for example, into a spreading code sequence having a rate of 1 Mcps, for example, so as to carry out a spectrum spreading, and a radio transmission is made from a transmitter 82. At a receiving end, a spectrum spread radio wave is received by a receiver 85, and a spreading code sequence having the same pattern as that used at the transmitting end is generated by a spreading code generator 87. This spreading code sequence is multiplied to the received wave by a demodulator 86, so as to carry out a despreading and obtain the original information data. When carrying out this despreading, an input timing of the spreading code sequence within the received wave is detected by a searcher 88, in order to synchronize the spreading code sequence generated by the spreading code generator 87 and the spreading code sequence within the received wave. The searcher 88 instructs a generation timing of the spreading code generator 87 based on the detected input timing, so that the spreading code sequence generated by the spreading code generator 87 is synchronized to the spreading code sequence within the received wave.
FIG. 2 is a system block diagram showing an example of the construction of the searcher 88. For example, a 8-bit parallel input signal is input to a correlator 90. The correlator 90 includes a multi-stage shift register 91 successively input with the input signal, a memory 92 storing a part of the spreading code sequence, such as a pilot signal, multipliers 93, and an adder 94. Each multiplier 93 compares corresponding bits of the output sequence of the shift register 91 and the output sequence of the memory 92, and outputs a high-level signal when the corresponding bits of the compared output sequences match. More particularly, each multiplier 93 carries out an exclusive-OR operation on the corresponding bits of the two output sequences. The adder 94 adds outputs of each of the multipliers 93. According to the correlator 90, a maximum amplitude is output when the spreading code sequence within the received wave which is successively input matches the part of the spreading code sequence set in the memory 92. The input timing of the spreading code sequence within the received wave can be detected based on this maximum amplitude output.
For example, a 10-bit output value from the correlator 90 is squared in a multiplier 95 and is converted into a 20-bit power value, for example. This 20-bit power value is stored in a delay profile memory 97 via an adder 96, as a delay profile data. This delay profile data is generated by the adder 96 which carries out a cyclic integration of the power values which are successively input and a cumulative addition thereof.
According to the conventional searcher 88, the antilogarithms (true values) of the data are processed subsequent to the output of the correlator 90. For this reason, when a 10-bit correlation value is converted into a power value by obtaining the square of the correlation value, the data width of the power value is enlarged to 20 bits. As a result, the scale of the circuit which carries out the operation becomes large, and the operation speed becomes slow. In addition, a memory capacity required to store the delay profile data becomes large.
Consequently, the data width of the power value is reduced by deleting the lower 10 bits of the 20-bit power value, for example. But when only the upper 10 bits of the power value are processed, there is a problem in that a dynamic range of the data inevitably becomes small.
In addition, even in the case of the power value having the data width of 20 bits, the dynamic range of the data is only 60 dB, for example, and there are demands to further improve the dynamic range of the data.
On the other hand, the problems described above not only occurs when converting the correlator output value into the power value, but similar problems also occur when a search operation is carried out by using the correlator output value as it is. Hence, there are demands to carry out the search operation by utilizing a correlator output value which has a small data width but has a large dynamic range.
Accordingly, it is a general object of the present invention to provide a novel and useful searcher for a CDMA receiver apparatus, in which the problems described above are eliminated and the demands described above are satisfied.
Another and more specific object of the present invention is to provide a searcher for a CDMA receiver apparatus, wherein information related to a correlation value which is used or a search operation is subjected to a non-linear processing, so as to reduce the number of bits of the correlation value while enlarging a dynamic range of the correlation value, so that the dynamic range becomes equivalent to or larger than a dynamic range which would be obtained when processing antilogarithms of the data.
Still another object of the present invention is to provide a searcher for a CDMA receiver apparatus, comprising a correlator obtaining a correlation value between a spreading code sequence and a spreading code sequence within a received signal, and a non-linear processor carrying out a non-linear conversion to convert one of the correlation value and a predetermined value indicative of the correlation value into correlation value information which has a data width smaller than that of the one of the correlation value and the predetermined value, where the correlation value information is used to carry out a search process to search for a synchronizing timing with respect to the spreading code sequence within the received signal. According to the searcher of the present invention, it is possible to reduce the data width (number of bits) while enlarging the dynamic range to a range equivalent to or greater than the dynamic range which is obtained when the data is treated in the form of the antilogarithm. Furthermore, it is possible to reduce the scale of the circuit and improve the operation speed of the searcher by carrying out the search operation using such data having the reduced data width.
A further object of the present invention is to provide a searcher for a CDMA receiver apparatus, comprising a correlator obtaining a correlation value between a spreading code sequence and a spreading code sequence within a received signal, a non-linear processor carrying out a non-linear conversion to convert the correlation value into a value which has a data width smaller than that of the correlation value, and a power value converter converting the value obtained from the non-linear processor into a power value and outputting the power value as correlation value information, where the correlation value information is used to carry out a search process to search for a synchronizing timing with respect to the spreading code sequence within the received signal. According to the searcher of the present invention, it is possible to reduce the data width (number of bits) while enlarging the dynamic range to a range equivalent to or greater than the dynamic range which is obtained when the data is treated in the form of the antilogarithm. Furthermore, it is possible to reduce the scale of the circuit and improve the operation speed of the searcher by carrying out the search operation using such data having the reduced data width.
Another object of the present invention is to provide a searcher having either one of the constructions described above, where non-linear conversion includes a logarithmic conversion of an input value into a value having a data width smaller than that of the input value. In other words, a process using logarithmic or n-th root (X1/n) is carried out, where the base of the logarithm is not limited to a specific value. Of course, the dynamic range can be varied depending on the base which is used. Typically, the base is 10, e (2.7182), or the like, and the dynamic range becomes wider as the value of the base becomes larger.
Still another object of the present invention is to provide a CDMA receiver apparatus comprising a generator generating a spreading code, and a searcher controlling a generation timing of the generator, where the searcher comprises a correlator obtaining a correlation value between a spreading code sequence and a spreading code sequence within a received signal, and a non-linear processor carrying out a non-linear conversion to convert one of the correlation value and a predetermined value indicative of the correlation value into correlation value information which has a data width smaller than that of the one of the correlation value and the predetermined value, and the correlation value information is used to carry out a search process to search for a synchronizing timing with respect to the spreading code sequence within the received signal. According to the CDMA receiver apparatus of the present invention, it is possible to reduce in the searcher the data width (number of bits) while enlarging the dynamic range to a range equivalent to or greater than the dynamic range which is obtained when the data is treated in the form of the antilogarithm. Furthermore, it is possible to reduce the scale of the circuit and improve the operation speed of the searcher by carrying out the search operation using such data having the reduced data width.